Recently, portable electronic equipment such as mobile telephones and non-volatile semiconductor memory media such as IC memory cards have been downsized, and there have been increasing demands for reducing the number of parts used in the equipment and media and downsizing thereof. Therefore, in the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability. For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting reliability places importance on packaging technologies that are capable of enhancing efficiency of a mounting process and improving mechanical and electrical reliability after the mounting process is completed. Thus, there have been considerable activities in the development of efficiently packaging a semiconductor chip. As packages that meet the demands, there are a chip scale package (CSP) having a package size substantially equal to that of the semiconductor chip, a multi-chip package (MCP) in which multiple semiconductor chips are incorporated into a single package, and a package-on-package (POP) in which multiple packages are stacked and combined into a single-piece member.
In pace with the development of technology, in response to an increase in storage capacity required for memory and the like, stacked type semiconductor devices (multichip devices) have been proposed which have semiconductor integrated circuit chips stacked together. Namely, there is provided a stacked type semiconductor device formed of at least two semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein each of the semiconductor integrated circuit devices includes a conductor that penetrates the semiconductor integrated circuit device, and the semiconductor integrated circuit devices are electrically connected by the conductors and a value of the specification, excluding a size, of the uppermost semiconductor integrated circuit device or the lowermost semiconductor integrated circuit device is maximum or minimum. Consequently, the stacked type semiconductor device has a plurality of chips stacked in a vertical direction. In the stacked type semiconductor device, the chips are electrically connected together via, for example, through plugs that penetrate the chips. Thus, to select a desired one of the stacked memory chips of the same structure is an important task. If a stacked type semiconductor device is manufactured, chips may be individually subjected to operation tests so that only normal chips can be sorted out and stacked.
One of the technologies to offer vertical connection is called Through-Silicon-Via (TSV) which has emerged as a promising solution in 3D stacked devices. It is a technology where vertical interconnects are formed through the wafer to enable communication among the stacked chips. TSV is 3D IC technique for signal transmission. It's a vertical electrical connection passing completely through a silicon wafer or die. People believe that 3D IC with TSV technique is the future design. It can help the IC process break its physical limit of shrinking and IC developments keep up with the Moore's Law. Features of TSV describes as follow: 1). 3D TSV signal transmission has smaller RC (Resistance multiply capacitance) loading compared with 2D global metal routing; 2). using TSV technique, chip can have higher performance; 3). TSV has large capacitance and small resistance; and 4). large capacitance would cause large energy consumption.
To address the above shortcomings, the invention's scheme and method are proposed.